This invention relates generally to the area of system interconnect technology.
As CPU speeds have reached the multi-gigahertz range, system designers increasingly focus on system interconnect as the primary bottleneck at the chip-to-chip, board-to-board, backplane and box-to-box levels. System interconnect has evolved from utilizing parallel I/O technology with source-synchronous clocking or system-synchronous clocking to multi-gigabit serial I/O with clock-data recovery (“CDR”). Channel aggregation bonds individual serial I/O lanes to create a multi-lane link, transcending the bandwidth limitations of single transceiver channels and providing the high bandwidth required by next generation serial protocols such as 40/100 Gigabit Ethernet and PCI Express Gen 3. However, various communication protocols have different functional requirements. At the same time, there is an increasing need for system designers to have flexibility in designing systems to work with one particular protocol versus another.
Scrambling/descrambling processing stages in a high speed transceiver allow high speed signals to have sufficient transition densities to help minimize data errors. Scrambling is typically carried out by linear feedback shift register (“LFSR”) circuits including shift register elements and one or more XOR circuits. However, different protocols have different scrambling techniques. For example, some protocols use multiplicative scrambling while others use additive scrambling. As another example, different protocols use different scrambling polynomials, each of which require different couplings to XOR circuits in an LFSR. Also, in some protocols lanes are aggregated and data across multiple lanes is preferably scrambled together. As another example, some protocols use a least significant bit (“LSB”) ordering of data while others use a most significant bit (“MSB”) ordering.
There is a need for integrated circuits (“ICs”) with transceivers that can be adapted for use with different protocols. However, it may be cumbersome/costly to provide completely separate scrambling circuitry for each possible protocol for which the IC might be utilized. Therefore, there is a need for scrambling circuitry that can be adapted for different protocols.